computer-architecture

49 entries in Formal Languages & Compilers.

• Two-bit saturating counterBimodal prediction tablestandardcomputer-architecture
• Gshare predictorGlobal history XOR indexingstandardcomputer-architecture
• Tournament predictorLocal-global chooserstandardcomputer-architecture
• TAGE predictorTagged geometric history lengthsspecialistcomputer-architecture
• Perceptron branch predictorLinear history weightsspecialistcomputer-architecture
• Return address stackCall-return pairingspecialistcomputer-architecture
• Branch target bufferTarget caching by addressstandardcomputer-architecture
• Tomasulo's algorithmReservation stations with register renamingcanonfull lesson ▸computer-architecture
• ScoreboardingCentralized hazard trackingstandardcomputer-architecture
• Reorder bufferIn-order commitstandardcomputer-architecture
• Register renamingPhysical register file mappingstandardcomputer-architecture
• Memory disambiguationStore-set predictorspecialistcomputer-architecture
• Store-to-load forwardingStore queue matchingspecialistcomputer-architecture
• Software pipeliningModulo schedulingspecialistcomputer-architecture
• List instruction schedulingCritical-path prioritystandardcomputer-architecture
• Trace schedulingFrequent-path superblocksspecialistcomputer-architecture
• Loop unrollingBody replication with index adjustmentstandardcomputer-architecture
• Loop tilingCache-blocked iterationcanoncomputer-architecture
• Loop interchangeStride-minimizing orderstandardcomputer-architecture
• Automatic vectorizationDependence-tested SIMD wideningstandardcomputer-architecture
• Superword level parallelismIsomorphic statement packingspecialistcomputer-architecture
• Stride prefetcherConstant-delta detectionstandardcomputer-architecture
• Global history buffer prefetcherCorrelated address historyspecialistcomputer-architecture
• Best-offset prefetcherOffset score votingspecialistcomputer-architecture
• Next-line prefetchingstandalonestandardcomputer-architecture
• Set-associative cacheIndex-tag lookupcanoncomputer-architecture
• Victim cacheSmall fully-associative spill bufferspecialistcomputer-architecture
• Skewed-associative cachePer-way hash indexingspecialistcomputer-architecture
• RRIP replacementRe-reference interval predictionspecialistcomputer-architecture
• Pseudo-LRU replacementTree-bit approximationstandardcomputer-architecture
• Hawkeye replacementBelady-imitating learningspecialistcomputer-architecture
• MESI protocolSnooped state transitionscanoncomputer-architecture
• MOESI protocolOwner-state dirty sharingspecialistcomputer-architecture
• Directory-based coherenceSharer bit vectorsstandardcomputer-architecture
• Dragon protocolUpdate-on-write sharingspecialistcomputer-architecture
• FR-FCFS schedulingRow-hit first orderingstandardcomputer-architecture
• Bank-aware address mappingXOR bank interleavingspecialistcomputer-architecture
• Dimension-order routingXY turn restrictionstandardcomputer-architecture
• Wormhole switchingFlit-level bufferingspecialistcomputer-architecture
• Virtual channel allocationDeadlock-free channel classesspecialistcomputer-architecture
• Booth multiplicationRadix-4 recodingstandardcomputer-architecture
• Wallace tree multiplierCarry-save reductionspecialistcomputer-architecture
• Kogge-Stone adderParallel prefix carrystandardcomputer-architecture
• Carry-lookahead adderGenerate-propagate logiccanoncomputer-architecture
• SRT divisionRedundant quotient digitsspecialistcomputer-architecture
• Goldschmidt divisionMultiplicative convergencespecialistcomputer-architecture
• Simultaneous multithreadingPer-cycle thread interleavingstandardcomputer-architecture
• Runahead executionSpeculative miss-driven prefetchspecialistcomputer-architecture
• Speculative executionCheckpoint and rollbackstandardcomputer-architecture